The present invention relates to a method of fabricating a semiconductor device in which FETs are disposed in the memory cell region and peripheral circuit region thereof and, more particularly, to the reduction of process steps for adjusting a threshold value.
As higher-degree integration of a semiconductor is pursued in recent years, the process for adjusting a threshold value or the like is becoming more complicated.
By way of example, a conventional method of fabricating a semiconductor device in which FETs are provided in the memory cell region and peripheral circuit region thereof will be described below with reference to the drawings. FIGS. 9 are cross sections of a semiconductor device provided with a dynamic random access memory (DRAM) of FET structure which is being fabricated according to the conventional method. In the drawing, the memory cell region is on the left side of the substrate and the peripheral circuit region is on the right side thereof.
As shown in FIG. 9(a), a silicon dioxide film 2 is formed to the thickness of 20 nm on the silicon substrate 1 which was previously doped with a p-type impurity. Thereafter, a silicon nitride film 3 which is resistant to oxidation is deposited to the thickness of 160 nm. A photoresist film 4 with openings for future isolations is formed on the surface of the silicon nitride film 3.
Next, as shown in FIG. 9(b), dry etching is performed using CH.sub.2 F.sub.2 at a flow rate of 30 sccm, O.sub.2 at a flow rate of 15 sccm, and He as a coolant at a flow rate of 5 sccm under a gas pressure of 8 Pa with a power of 250 W, so that the silicon nitride film 3 in the openings of the photoresist mask 4 is vertically etched. Then, an impurity boron (B) for forming a channel stopper 5 is implanted into the resulting openings with energy of 80 KeV at a dose of 1.5.times.10.sup.13 /cm.sup.2. After that, the photo-resist mask 4 is removed.
Next, as shown in FIG. 9(c), an oxidation process is performed for 100 minutes at 1000.degree. C. so as to form the isolations 6 composed of so-called LOCOS. After that, the silicon nitride film 3 is removed.
Subsequently, as shown in FIG. 9(d), an impurity for threshold adjustment is introduced by ion implantation into a device formation region Rpr of the peripheral circuit region with the use of a photoresist mask 7 with an opening for the device formation region Rpr of the peripheral circuit region. After that, the photoresist mask 7 is removed.
Then, as shown in FIG. 9(e), the impurity for threshold adjustment is introduced by ion implantation into a device formation region Rmm of the memory cell region with the use of a photoresist mask 9. After that, the photoresist mask 9 is removed.
In the case where FETs are provided in the peripheral circuit region and memory cell region, respectively, it is necessary to maintain the threshold for the FET in the peripheral circuit region at a lower value in order to enhance the operating speed thereof. On the other hand, since the data holding property is crucial to the FET in the memory cell region, the leakage current when the power supply is off should be minimized. However, as the channel length is reduced with the miniaturization of the FET, a higher threshold value is required for this purpose.
However, when the impurity is introduced by a single implantation process, the threshold values for the FETs for both regions become equal. Therefore, it becomes necessary to individually perform ion implantations for adjusting the threshold value for the FET in the peripheral circuit region and for adjusting the threshold value for the FET in the memory cell region, which is disadvantageous in that an increased number of steps are required for processing.